| |
|
Intel Timna - 1999
Intel Timna, Intel's first system-on-a-chip attempt announced in March, 1999, is the project codename of an integrated Celeron chip combines a processor core, a Savage 4 GPU from S3 and an Intel I/O Controller Hub 2 (ICH2). It was designed for low-cost and mobile PCs. The project was hosted in Israel, so its name, Timna, came from an Israeli city. The processor core was based on Intel's Katmai core, which was used for the original Pentium III chips (up to 600MHz). Timna uses 15.2 watts of power compared with the 19.8 watts consumed by the Celeron/810 combination. Its memory controller was originally designed to work with RDRAM.
Due to RDRAM's much higher cost and lower availability, when compared with SDRAM, Intel later decided to ship Timna with the Memory Translator Hub (MTH, later renamed to Memory Protocol Translator), a small standalone chip which allows Timna to support standard SDRAM memory. The addition of MTH meant that Timna would access memory more slowly than a Celeron chip because of the translation needed between the CPU and SDRAM. Also, Intel encountered difficulty working out the final bugs of this memory transition; the bugs in the MTH emerged under a combination of electrical noise, voltage and temperature which leads to circuit failure. Moreover, Timna lacks some graphics capabilities such as optional display cache which hampers its 3D rendering performance.
Originally, Timna was estimated to cut the OEM manufacturing cost by US$30; on the other hand, the average price of Timna, if released on schedule, was about US$20 to US$30 more expensive than Celeron of the same working frequency. Computer manufacturers also expressed concerns that Timna's high integration left little room for differentiation. The standalone Celeron, combined with the 810 chip sets and integrated graphics, gave OEMs more design flexibility and the ability to design products with longer cycles while keeping the manufacturing cost comparable to Timna's; because of smaller motherboards and chipsets that integrate graphics, the cost savings had already been achieved using Celeron. Without the low-cost edge, it made Timna an extremely undesirable product given its low performance, inflexibility and the never ending delays. On top of the MTH problem and OEM resistance was a third issue: putting all the processor's component parts on a single die would seem to make for a large die size, a fact almost certain to lead to lower yields. Timna would have consumed more silicon than Celeron manufacturing in a 0.18-micron process. Although this problem could be solved when moving onto 0.13-micron process, it still meant that Intel would have used more silicon to manufacture its cheapest product. Under those conditions, Intel finally cancelled its work on Timna on September 29, 2000.
Intel Timna had a very short period of development time (less than two years) and was never released, so it is difficult to spot a Timna on the market given the fact that there is no motherboard available (except the ones display in Taipei Computex in 2000); not many collector even aware the existence of Timna. The Timna on the right is a 667Mhz engineering sample from Israel; only 5 of them surfaced so far.
| Process: |
0.18 micron |
| Package: |
Flip-Chip Pin Grid Array (FC-PGA) on 370-pin interposer (PGA370S) |
| Data Bandwidth: |
32 bit |
| Working Voltage: |
1.65V |
| Released Clock Speed(s) |
533MHz - 700MHz |
|
Intel Timna 667Mhz QV18 Engineering Sample (RB80529RZ667128) [F] [B]
Intel Timna 為英特爾於1999年三月公開的整合型晶片計畫名稱。這是英特爾首次嘗試將中央處理器晶片核心、S3的Savage 4繪圖晶片以及 Intel I/O 控制晶片 (ICH2)整合至同一晶片上。該晶片是針對行動及低價電腦所設計。這計畫是由位於以色列的實驗室所進行，所以該晶片的研發代號「Timna」實際上是以色列一個小城市名。Timna的中央處理器核心實際上是建構於之前的PentiumIII Katmai核心。相較於Celeron與810晶片組所消耗的19.8瓦，Timna僅使用15.2瓦的電力。其記憶體控制晶片原本是針對Rambus記憶體（RDRAM）所設計的。
相較於SD記憶體（SDRAM），Rambus記憶體的價格高出許多且產量較低，所以英特爾之後決定為Timna加上記憶編譯器（Memory Translator Hub，之後更名為記憶通訊協定編譯器），一個讓Timna可以與SDRAM溝通的小晶片。增加了這個記憶編譯器也意味著Timna處理器與記憶體之間的溝通會因為多了一道翻譯以及解譯的動作而拖慢整個傳輸速度，甚至比Celeron還慢。不久之後，英代爾發現在電訊噪音、電壓以及溫度的交互影響下會導致該記憶編譯器產生嚴重的電路錯誤，而英代爾一直無法找出設計上的錯誤並更正。不僅如此，Timna 的繪圖部分也缺少了一些像是選項顯示暫存等功能而影響到整個3D繪圖效率。
按照原本的計畫，Timna預計可以為代工廠省下約美金三十元的成本。不過另一方面，如果Timna如期推出，該晶片的售價卻會比同時脈的Celeron高出美金二十至三十元。電腦廠商也擔心這種整合型晶片會導致廠商的產品走向單一化。Celeron處理器、810晶片組加上整合繪圖晶片反而給予電腦廠商更多的空間來設計出不同的產品線以及更長的產品週期，而製造成本並不會因此而增加。實際上由於主機板越做越小而且更多晶片組已經有整合繪圖晶片，所以使用Celeron的生產成本已經下降許多。沒有了價格優勢，Timna的低效能、無法變更的系統配備（全部都在一塊晶片上）以及不斷延期，導致Timna在電腦廠商間已經變成了燙手山芋。除了記憶編譯器以及電腦廠商的反彈之外還有另一個大問題：把所有晶片整合在一起會使得晶片面積變大，這也就意味著生產量將會降低。在0.18-micro製程，Timna將會比Celeron消耗掉更多晶圓。當然這問題可以藉著將Timna推向0.13-micro製程而解決，但是這仍舊意味著英特爾會將較多的晶圓消耗在他們最低價的產品線上。基於這些理由，英特爾終於在2000年九月二十九日宣布中止Timna計畫。
Intel Timna 的研發週期極為短暫（不到兩年）而且還沒推出就胎死腹中，所以要在市面上找到Timna非常困難，連Timna的主機板都很難找（除了2000年台北電腦展的那些樣品）。實際上很少收集家知道TImna的存在（更不要說一般使用者了）。在右邊的這個 Timna是一個來自以色列的 667Mhz 工程樣品。目前同製程的產品只有大約五個現世。目前唯一有機會找到Timna的地方應該就是台灣跟以色列，尤其台灣主機板廠商在2000年已經有Timna的主機板展出，表示應該還有一些Timna鎖在台灣研發部門的某個櫃子裡。
| 製程: |
0.18 micron |
| 封裝: |
Flip-Chip Pin Grid Array (FC-PGA) on 370-pin interposer (PGA370S) |
| 資料頻寬: |
32 bit |
| 工作電壓: |
1.65V |
| 工作時脈: |
533MHz - 700MHz |
|
Intel Timna 667Mhz QV18 Engineering Sample (RB80529RZ667128) 正 反
|
|
|
|
|
|
